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?1 CXD3009Q 80 pin qfp (plastic) e97322c11 cd digital signal processor description the CXD3009Q is a digital signal processor lsi for cd players and is equipped with built-in digital filters, zero detection circuit, 1-bit dac, and analog low-pass filter on a single chip. features digital signal processor (dsp) block playback mode supporting cav (constant angular velocity) ? frame jitter-free ? allows 0.5 to double-speed continuous playback ? allows relative rotational velocity readout ? supports external spindle control wide capture range playback mode ? spindle rotational velocity following method ? supports normal-speed and double-speed playback 16k ram efm data demodulation enhanced efm frame sync protection sec strategy-based error correction subcode demodulation and sub q data error detection digital spindle servo 16-bit traverse counter asymmetry compensation circuit serial bus-based cpu interface error correction monitor signals, etc. are output from a new cpu interface. servo auto sequencer digital audio interface output digital peak meter cd-text data demodulation digital filter, dac, analog low-pass filter block dbb (digital bass boost) supports double-speed playback digital de-emphasis digital attenuation function zero detection function 8fs oversampling digital filter applications cd players structure silicon gate cmos ic absolute maximum ratings supply voltage v dd ?.3 to +4.6 v input voltage v i ?.3 to +4.6 v (vss ?0.3v to v dd + 0.3v) output voltage v o ?.3 to +4.6 v storage temperature tstg ?0 to +125 ? supply voltage difference v ss ?av ss ?.3 to +0.3 v v dd ?av dd ?.3 to +0.3 v note) av dd includes xv dd , and av ss includes xv ss . recommended operating conditions supply voltage v dd 2.5 to 3.6 v operating temperature topr ?0 to +75 ? input/output capacitances input capacitance c i 12 (max.) pf output capacitance c o 12 (max.) pf note) measurement conditions v dd = v i = 0v f m = 1mhz sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits.
?2 CXD3009Q block diagram efm demodurator clock generator osc error corrector d/a interface serial-in interface over sampling digital filter timing logic 3rd-order noise shaper pwm pwm 16k ram digital out digital clv cpu interface servo auto sequencer asymmetry corrector digital pll sub code processor c4m rf asyi asyo bias xpck filo fili pco cltv fok sein cnin dato xlto clko sens data xlat clok xlon scor sbso exck sqso sqck mdp dout lout2 ain2 aout2 lout1 ain1 aout1 xtsl vpco vcki v16m vctl xugf gfs emph wfck c2po lrck pcmd bck emphi lrcki pcmdi bcki sysm rmut lmut xtai xtao pwmi xrst test tes1 spoa spob 40 39 38 37 36 35 31 33 41 42 43 44 47 48 49 50 51 52 53 54 55 56 57 58 59 70 67 65 66 62 71 74 75 76 79 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 21 23 24 25 26 27 28 29 30 22
3 CXD3009Q pin configuration 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 v dd sysm avss av dd aout1 ain1 lout1 avss xv dd xtai xtao xvss avss lout2 ain2 aout2 av dd avss xrst v dd lrcki lrck asyo asyi bias rf av dd cltv mdp avss fili filo pco vctl v16m vcki vpco pwmi vss exck sbso emphi dout c4m pcmd xpck xugf v dd vss bcki bck scor wfck c2po gfs emph xtsl pcmdi lmut sens xlat sqso rmut sqck data sein vss clok vss cnin dato xlto clko spoa spob xlon fok v dd tes1 test
4 CXD3009Q pin description pin no. symbol i/o description gnd left-channel zero detection flag. right-channel zero detection flag. sqso readout clock input. sub q 80-bit serial output. sens output to cpu. serial data input from cpu. latch input from cpu. serial data is latched at the falling edge. serial data transfer clock input from cpu. sens input from ssp. track jump count signal input. serial data output to ssp. serial data latch output to ssp. latched at the falling edge. serial data transfer clock output to ssp. microcomputer extended interface (input a). microcomputer extended interface (input b). microcomputer extended interface (output). focus ok input. used for sens output and the servo auto sequencer. power supply (+3v). gnd spindle motor servo control. spindle motor external control input. test pin; normally gnd. test pin; normally gnd. charge pump output for the wide-band efm pll. vco2 oscillation input for the wide-band efm pll. vco2 oscillation output for the wide-band efm pll. vco2 control voltage input for the wide-band efm pll. master pll charge pump output. master pll (slave = digital pll) filter output. master pll filter input. analog gnd. master vco control voltage input. analog power supply (+3v). efm signal input. 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, z, 0 1, z, 0 1, 0 1, z, 0 analog o o i o o i i i i i o o o i i o i o i i i o i o i o o i i i v ss lmut rmut sqck sqso sens data xlat clok sein cnin dato xlto clko spoa spob xlon fok v dd v ss mdp pwmi test tes1 vpco vcki v16m vctl pco filo fili av ss cltv av dd rf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
5 CXD3009Q pin no. symbol i/o description constant current input of the asymmetry circuit. asymmetry comparator voltage input. efm full-swing output (low = v ss , high = v dd ). d/a interface. lr clock output f = fs. lr clock input. d/a interface. serial data output (two's complement, msb first). d/a interface. serial data input (two's complement, msb first). d/a interface. bit clock output. d/a interface. bit clock input. gnd power supply (+3v). xugf output. switched to mnt1 or rfck output by a command. xplck output. switched to mnt0 output by a command. gfs output. switched to mnt3 or xraof output by a command. c2po output. switched to gtop output by a command. crystal selector input. low: 16.9344mhz; high: 33.8688mhz. 4.2336mhz output. 1/4 frequency-divided vcki output in cav-w mode. digital out output. outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. inputs a high signal when de-emphasis is on, and a low signal when de-emphasis is off. wfck output. outputs a high signal when either subcode sync s0 or s1 is detected. sub p to w serial output. sbso readout clock input. gnd power supply (+3v). mute input. active when high. analog gnd. analog power supply (+3v). left-channel analog output. left-channel operational amplifier input. left-channel line output. analog gnd. power supply for master clock. crystal oscillation circuit input. input the external master clock via this pin. crystal oscillation circuit output. 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 i i o o i o i o i o o o o i o o o i o o o i i o i o i o bias asyi asyo lrck lrcki pcmd pcmdi bck bcki v ss v dd xugf xpck gfs c2po xtsl c4m dout emph emphi wfck scor sbso exck v ss v dd sysm av ss av dd aout1 ain1 lout1 av ss xv dd xtai xtao 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
6 CXD3009Q pin no. symbol i/o description gnd for master clock. analog gnd. right-channel line output. right-channel operational amplifier input. right-channel analog output. analog power supply (+3v). analog gnd. system reset. reset when low. power supply (+3v). o i o i xv ss av ss lout2 ain2 aout2 av dd av ss xrst v dd 72 73 74 75 76 77 78 79 80 notes) pcmd is an msb first, two's complement output. gtop is used to monitor the frame sync protection status. (high: sync protection window open.) xugf is the frame sync obtained from the efm signal, and a negative pulse. it is the signal before sync protection. xplck is the inverse of the efm pll clock. the pll is designed so that the falling edge of xplck and the efm signal transition point coincide. gfs goes high when the frame sync and the insertion protection timing match. rfck is derived with the crystal accuracy. this signal has a cycle of 136s (during normal speed). c2po represents the data error status. xraof is generated when the 16k ram exceeds the 4f jitter margin.
7 CXD3009Q electrical characteristics dc characteristics (v dd = av dd = 3.3v 5%, v ss = av ss = 0v, topr = 20 to +75 c) ? item input voltage (1) input voltage (2) input voltage (3) output voltage (1) output voltage (2) output voltage (4) input leak current tri-state pin output leak current ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 1, ? 2, ? 3 schmitt input analog input i oh = 4ma i ol = 4ma i oh = 2ma i ol = 4ma i oh = 0.28ma i ol = 0.36ma v i = 0 to 3.60v v o = 0 to 3.60v high level input voltage low level input voltage high level input voltage low level input voltage input voltage high level output voltage low level output voltage high level output voltage low level output voltage high level output voltage low level output voltage v ih (1) v il (1) v ih (2) v il (2) v in (3) v oh (1) v ol (1) v oh (2) v ol (2) v oh (4) v ol (4) i li i lo 0.7v dd 0.7v dd vss v dd 0.4 0 v dd 0.4 0 v dd 0.4 0 5 5 0.2v dd 0.2v dd v dd v dd 0.4 v dd 0.4 v dd 0.4 5 5 v v v v v v v v v v v a a conditions min. typ. max. unit applicable pins applicable pins ? 1 xtsl, data, xlat, pwmi, sysm, emphi, pcmdi ? 2 clok, xrst, exck, sqck, fok, sein, cnin, vcki, lrcki, bcki, spoa, spob ? 3 cltv, fili, rf, vctl, ain1, ain2 ? 4 mdp, pco, vpco ? 5 asyo, dout, c4m, sbso, sqso, scor, emph, dato, clko, xlto, sens, wfck, v16m, lmut, rmut, xlon, lrck, pcmd, bck, xugf, xpck, gfs, rfck, c2po ? 6 filo ? 7 sens, pco, vpco ? note) : xv dd and xv ss are included for av pp and av ss , respectively. those are the same for the explanation from the next page.
ac characteristics 1. xtai pin (1) when using self-excited oscillation (topr = 20 to +75 c, v dd = av dd = 3.3v 5%) (2) when inputting pulses to xtai pin (topr = 20 to +75 c, v dd = av dd = 3.3v 5%) (3) when inputting sine waves to xtai pin via a capacitor (topr = 20 to +75 c, v dd = av dd = 3.3v 5%) 8 CXD3009Q oscillation frequency f max 7 34 mhz item symbol min. typ. max. unit high level pulse width t whx 13 500 ns low level pulse width t wlx 13 500 ns pulse cycle t ck 26 1,000 ns input high level v ihx 0.7v dd v input low level v ilx 0.2v dd v rise time, fall time t r , t f 10 ns item symbol min. typ. max. unit input amplitude v 1 0.5v dd v dd + 0.3 vp-p item symbol min. typ. max. unit t r t f t whx t wlx t ck v ilx v ihx 0.1 v ihx 0.9 v ihx xtai v dd /2
9 CXD3009Q 2. clok, data, xlat, cnin, sqck and exck pins (v dd = av dd = 3.3v 5%, v ss = av ss = 0v, topr = 20 to +75 c) ? in pseudo double-speed playback mode, except when sqso is sub q read, the maximum operating frequency for sqck is 300khz and the minimum pulse width is 1.5s. 3. bcki, lrcki and pcmdi pins (v dd = av dd = 3.3v 5%, v ss = av ss = 0v, topr = 20 to +75 c) clock frequency clock pulse width setup time hold time delay time latch pulse width exck sqck frequency exck sqck pulse width f ck t wck t su t h t d t wl f t f wt 750 300 300 300 750 750 ? 0.65 0.65 ? mhz ns ns ns ns ns mhz ns item symbol min. typ. max. unit t wck t wck 1/f ck t h t su t wl t d 1/f t t wt t wt t h t su clk data xlt exck cnin sqck sqso sbso bck pulse width datal, r setup time datal, r hold time lrck setup time t w t su t h t su ns ns ns ns item symbol conditions typ. 94 18 18 18 min. max. unit v dd /2 v dd /2 t w (bcki) t w (bcki) t su (pcmdi) t h (pcmdi) t su (lrcki) bcki pcmdi lrcki
10 CXD3009Q 1-bit dac, lpf block analog characteristics analog characteristics (v dd = av dd = 3.3v, v ss = av ss = 0v, ta = 25 c) for both items, fs = 44.1khz. the total harmonic distortion and s/n ratio measurement circuits are shown below. lpf external circuit diagram block diagram for measuring analog characteristics item total harmonic distortion s/n ratio symbol thd s/n conditions 1khz, 0db data crystal 1khz, 0db data (using a-weighting filter) 384fs 768fs 384fs 768fs 90 90 0.015 0.015 94 94 0.025 0.025 min. typ. max. unit % db audio analyzer shibasoku (am51a) 100k 22 680p 12k 12k 12k 150p aout1 (2) ain1 (2) lout1 (2) audio analyzer CXD3009Q rch a lch b data rf test disc 768fs/384fs
11 CXD3009Q (v dd = av dd = 3.3v, v ss = av ss = 0v, topr = 20 to +75 c) output voltage load resistance v out r l ? 1 ? 1 vrms k ? item symbol 20 min. max. 0.70 ? typ. applicable pins unit ? measured using the circuits on the previous page when a sine wave of 1khz and 0db is output. applicable pins ? 1 lout1, lout2
12 CXD3009Q description of functions 1. cpu interface and commands cpu interface this interface uses data, clok and xlat to set the modes. the interface timing chart is shown below. information on each address and the data is provided in table 1-1. the internal registers are initialized by a reset when xrst is low; the initialization data is shown in table 1-2. note) when xlat is low, sqck must be set high. 750ns or more data address 750ns or more 300ns max valid clok data xlat registers 4 to e d1 d2 d3 d0 d1 d2 d3
13 CXD3009Q command table table 1-1 register name 4 5 6 7 8 9 a b c d e auto sequence blind (a, e), overflow (c) brake (b) kick (d) auto sequence (n) track jump count mode specification function specification audio ctrl serial bus ctrl servo coefficient setting clv ctrl clv mode 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 2048 vco sel1 0 0 0 0 trmi vp7 epwm 1024 0 0 0 0 0 trmo vp6 spdc 512 soct 0 0 opsl2 0 opsl2 1 mtsl1 vp5 icap 256 vco sel2 sycof sycof emph emph mtsl0 vp4 sfsl 128 ksl3 opsl1 0 opsl1 1 smut smut 0 vp3 vc2c 64 ksl2 mcsl mcsl ad10 ad10 0 vp2 hifc 32 ksl1 0 0 ad9 ad9 0 vp1 lpwr 16 ksl0 0 0 ad8 ad8 0 vp0 vpon 8 0 zdpl zdpl ad7 ad7 gain cav1 4 0 zmut zmut ad6 ad6 gain cav0 2 vco2 thru 0 ad5 ad5 0 1 0 0 ad4 ad4 0 0 0 ad3 ad3 0 dcof ad2 ad2 0 0 ad1 ad1 0 0 ad0 ad0 txon fmut txout lrwo outl1 bsbst outl0 bbsl as3 0.18ms 0.36ms 11.6ms 32768 cdrom 0 0 0 0 sl1 gain mdp1 0 cm3 as2 0.09ms 0.18ms 5.8ms 16384 dout mute dspb on/off dspb on/off 0 0 sl0 gain mdp0 tb cm2 as1 0.05ms 0.09ms 2.9ms 8192 dout on/off 0 0 mute mute cpusr gain mds1 tp cm1 as0 0.02ms 0.05ms 1.45ms 4096 wsel 0 0 att att 0 gain mds0 gain clvs cm0 command address d3 d2 d1 d0 data 1 d3 d2 d1 d0 data 2 d3 d2 d1 d0 data 3 d3 d2 d1 d0 data 4 d3 d2 d1 d0 data 5 d3 d2 d1 d0 data 6 d3 d2 d1 d0
14 CXD3009Q reset initialization table 1-2 register name 4 5 6 7 8 9 a b c d e auto sequence blind (a, e), overflow (c) brake (b) kick (d) auto sequence (n) track jump count setting mode specification function specification audio ctrl serial bus ctrl servo coefficient setting clv ctrl clv mode 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 command address d3 d2 d1 d0 data 1 d3 d2 d1 d0 data 2 d3 d2 d1 d0 data 3 d3 d2 d1 d0 data 4 d3 d2 d1 d0 data 5 d3 d2 d1 d0 data 6 d3 d2 d1 d0
15 CXD3009Q 1-1. the meaning of the data for each address is explained below. $4x commands rxf = 0 forward rxf = 1 reverse when the focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. when the track jump/move commands ($48 to $4f) are canceled, $25 is sent and the auto sequence is interrupted. $5x commands auto sequence timer setting setting timers: a, e, c, b ex.) d2 = d0 = 1, d3 = d1 = 0 (initial reset) a = e = c = 0.11ms b = 0.23ms $6x commands auto sequence timer setting setting timer: d ex.) d3 = 0, d2 = d1 = d0 = 1 (initial reset) d = 10.15ms $7x commands auto sequence track jump/move count setting (n) this command is used to set n when a 2n-track jump and an n-track move are executed for auto sequence. the maximum track count is 65,535, but note that with 2n-track jumps the maximum track jump count is determined by the mechanical limitations of the optical system. the number of tracks jumped is counted according to the signals input from the cnin pin. cancel focus-on 1 track jump 10 track jump 2n track jump n track move 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 rxf rxf rxf rxf command as3 as2 as1 as0 blind (a, e), over flow (c) brake (b) 0.18ms 0.36ms 0.09ms 0.18ms 0.05ms 0.09ms 0.02ms 0.05ms command d3 d2 d1 d0 kick (d) 11.6ms 5.8ms 2.9ms 1.45ms command command data 1 data 2 data 3 data 4 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 auto sequence track jump count setting d3 d2 d1 d0
16 CXD3009Q command d3 cdrom dout mute dout on/off wsel vco sel1 0 soct vco sel2 ksl3 ksl2 ksl1 ksl0 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 1 data 2 mode specification data 3 command bit c2po timing cdrom = 1 cdrom = 0 see timing chart 1-1. see timing chart 1-1. cdrom mode; average value interpolation and pre-value hold are not performed. audio mode; average value interpolation and pre-value hold are performed. processing command bit dout mute = 1 dout mute = 0 digital out output is muted. (da output is not muted.) when no other mute conditions are set, digital out output is not muted. processing $8x commands command bit dout on/off = 1 dout on/off = 0 digital out is output from the dout pin. digital out is not output from the dout pin. processing command bit sync protection window width wsel = 1 wsel = 0 26 channel clock ? 1 6 channel clock anti-rolling is enhanced. sync window protection is enhanced. application see the $bx commands. ? 1 in normal-speed playback, channel clock = 4.3218mhz. d3 00 vco2 thru 0 0 0 0 0 txon txout outl1 outl0 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 4 data 5 data 6
17 CXD3009Q command bit vcosel1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 multiplier pll vco1 is set to normal speed, and the output is 1/1 frequency-divided. multiplier pll vco1 is set to normal speed, and the output is 1/2 frequency-divided. multiplier pll vco1 is set to normal speed, and the output is 1/4 frequency-divided. multiplier pll vco1 is set to normal speed, and the output is 1/8 frequency-divided. multiplier pll vco1 is set to high speed ? 1 , and the output is 1/1 frequency-divided. multiplier pll vco1 is set to high speed ? 1 , and the output is 1/2 frequency-divided. multiplier pll vco1 is set to high speed ? 1 , and the output is 1/4 frequency-divided. multiplier pll vco1 is set to high speed ? 1 , and the output is 1/8 frequency-divided. ksl3 ksl2 processing ? 1 approximately twice the normal speed. command bit vcosel2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 wide-band pll vco2 is set to normal speed, and the output is 1/1 frequency-divided. wide-band pll vco2 is set to normal speed, and the output is 1/2 frequency-divided. wide-band pll vco2 is set to normal speed, and the output is 1/4 frequency-divided. wide-band pll vco2 is set to normal speed, and the output is 1/8 frequency-divided. wide-band pll vco2 is set to high speed ? 2 , and the output is 1/1 frequency-divided. wide-band pll vco2 is set to high speed ? 2 , and the output is 1/2 frequency-divided. wide-band pll vco2 is set to high speed ? 2 , and the output is 1/4 frequency-divided. wide-band pll vco2 is set to high speed ? 2 , and the output is 1/8 frequency-divided. ksl1 ksl0 processing ? 2 approximately twice the normal speed.
18 CXD3009Q command bit txout = 0 processing various signals except cd-text are output from sqso pin. see $bx commands. cd-text data is output from sqso pin. ? see "4-9. cd-text data demodulation". txout = 1 command bit outl1 = 0 processing wfck, xpck and c4m are output. wfck, xpck and c4m outputs are set to low. outl1 = 1 command bit outl0 = 0 outl0 = 1 processing pcmd, bck, lrck and emph are output. pcmd, bck, lrck and emph outputs are set to low. pcmd and pcmdi, bck and bcki, lrck and lrcki, emph and emphi are connected inside the ic, respectively. at this time, set pcmdi = bcki = lrcki = emphi = low. command bit vco2 thru = 0 processing v16m output is connected to vcki inside the ic. set vcki to low in this time. v16m output is not connected to vcki inside the ic. input the clock from vcki in this time. ? these commands are used to set the internal or external connection of vco2 used in cav-w mode. vco2 thru = 1 command bit txon = 0 processing set txon to 0 when the cd-text data is not demodulated. set txon to 1 when the cd-text data is demodulated. ? see "4-9. cd-text data demodulation". txon = 1
19 CXD3009Q timing chart 1-1 rch 16-bit c2 pointer lch 16-bit c2 pointer if c2 pointer = 1, data is ng c2 pointer for upper 8-bits c2 pointer for lower 8-bits rch c2 pointer c2 pointer for upper 8-bits c2 pointer for lower 8-bits lch c2 pointer lrck cdrom = 0 cdrom = 1 c2po c2po
20 CXD3009Q $9x commands (opsl1= 0) ? data 2 d0 and subsequent data are df/dac function settings. command bit dspb = 1 dspb = 0 double-speed playback (cd-dsp block) normal-speed playback (cd-dsp block) processing command bit sycof = 1 sycof = 0 lrck asynchronous mode normal operation processing command bit opsl1 = 1 opsl1 = 0 dcof can be set. dcof cannot be set. processing command bit mcsl = 1 mcsl = 0 df/dac block master clock selection. crystal = 768fs (33.8688mhz) df/dac block master clock selection. crystal = 384fs (16.9344mhz) processing command data 1 d3 0 dspb on/off 0 0 0 mcsl 0 0 zdpl zmut d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 3 data 4 data 2 function specification 000 sycof d3 to d1 d0 opsl1 d3 d2 d1 d0 data 5 $9x commands (opsl1= 1) ? data 2 d0 and subsequent data are df/dac function settings. command data 1 d3 0 dspb on/off 0 0 1 mcsl 0 0 zdpl zmut 0 0 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 3 data 4 data 2 function specification 000 sycof d3 to d1 d0 opsl1 d3 0 dcof 0 0 d2 d1 d0 data 5 ? set sycof = 0 in advance when setting the $ax command lrwo to 1.
21 CXD3009Q command bit zdpl = 1 zdpl = 0 lmut and rmut pins are high when muted. lmut and rmut pins are low when muted. processing ? see "mute flag output" for the mute flag output conditions. command bit dcof = 1 dcof = 0 dc offset is off. dc offset is on. processing ? dcof can be set when opsl1 = 1. ? set dc offset to off when zero detection mute is on. command bit zmut = 1 zmut = 0 zero detection mute is on. zero detection mute is off. processing $ax commands (opsl2 = 0) ? data 2 and subsequent data are df/dac function settings. command data 1 d3 0 0 mute att 0 0 0 emph d2 d1 d0 d3 d2 d1 d0 data 2 data 3 audio ctrl smut ad10 d3 d2 opsl2 data 4 d3 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 5 data 6 data 3 ad9 ad8 d1 d0 $ax commands (opsl2 = 1) ? data 2 and subsequent data are df/dac function settings. command data 1 d3 0 0 mute att 0 0 1 emph d2 d1 d0 d3 d2 d1 d0 data 2 data 3 audio ctrl smut ad10 d3 d2 opsl2 data 4 d3 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 fmut lrwo bsbst bbsl d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 5 data 6 data 3 ad9 ad8 d1 d0
22 CXD3009Q the attenuation data consists of 10 bits, and is set as follows. attenuation data 400h 3ffh 3feh : 001h 000h 0db 0.0085db 0.017db 60.206db audio output command bit emph = 1 emph = 0 de-emphasis is on. de-emphasis is off. processing ? if either the emphi pin or emph is high, de-emphasis is on. ? if either the smut pin or smut is high, soft mute is on. command bit smut = 1 smut = 0 soft mute is on. soft mute is off. processing command bit ad9 to 0 attenuation data. meaning command bit mute = 1 mute = 0 cd-dsp block mute is on. 0 data is output from the cd-dsp block. cd-dsp block mute is off. processing command bit att = 1 att = 0 cd-dsp block output is attenuated ( 12db). cd-dsp block attenuation is off. processing command bit opsl2 = 1 opsl2 = 0 fmut, lrwo, bsbst and bbsl can be set. fmut, lrwo, bsbst and bbsl cannot be set. meaning the attenuation data (ad10 to ad0) consists of 11bits, and can be set in 1024 different ways. the audio output from 001h to 400h is obtained using the following equation. audio output = 20log [db] attenuation data 1024
23 CXD3009Q command bit fmut = 1 fmut = 0 forced mute is on. forced mute is off. meaning ? fmut can be set when opsl2 = 1. command bit bsbst = 1 bsbst = 0 bass boost is on. bass boost is off. processing ? bsbst can be set when opsl2 = 1. command bit bbsl = 1 bbsl = 0 bass boost is max. bass boost is mid. processing ? bbsl can be set when opsl2 = 1. command bit lrwo = 1 lrwo = 0 forced synchronization mode note ) normal operation. meaning ? lrwo can be set when opsl2 = 1. note) synchronization is performed at the first falling edge of lrck during reset, so there is normally no need to set this mode. however, synchronization can be forcibly performed by setting lrwo = 1.
24 CXD3009Q command d3 sl1 sl0 cpusr 0 d2 d1 d0 trm1 d3 trm0 d2 mtsl1 d1 mtsl0 d0 data 1 data 2 serial bus ctrl $bx commands soct 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 subq peak meter sens d subq a b c sl1 sl0 mode the sqso pin output can be switched to the various signals by setting the soct command of $8x and the sl1 and sl0 commands of $bx. set sqck to high at the falling edge of xlat. except for sub q and peak meter, the signals are loaded to the register when they are set at the falling edge of xlat. sub q is loaded to the register with each scor, and peak meter is loaded when a peak is detected. mode a xlat sqck mode b mode c mode d peak meter vf0 vf1 vf2 vf3 vf4 vf5 vf6 vf7 alock c1f1 c1f2 0 c2f1 0 c2f2 fok lock gfs emph per1 per2 per3 per4 per5 per6 per7 per0 c1f1 c1f2 0 c2f1 0 c2f2 fok lock gfs emph 0 per1 per2 per3 per4 per5 per6 per7 c1f1 0 c1f2 c2f1 0 c2f2 fok lock gfs emph vf0 alock vf1 vf2 vf3 vf4 vf5 vf6 vf7 per0 spoa c1f1 c1f2 c2f1 c2f2 xraof fok gfs l0 l1 l2 l3 l4 l5 l6 l7 r0 r1 r2 r3 r4 r5 r6 r7 lock emph rfck wfck scor 0 0 spob gtop
25 CXD3009Q signal per0 to 7 fok gfs lock emph alock vf0 to 7 spoa, b wfck scor gtop rfck xraof l0 to l7, r0 to r7 rf jitter amount (used to adjust the focus bias). 8-bit binary data in per0 = lsb, per7 = msb. focus ok high when the frame sync and the insertion protection timing match. gfs is sampled at 460hz; when gfs is high, a high signal is output. if gfs is low eight consecutive samples, a low signal is output. high when the playback disc has emphasis. gfs is sampled at 460hz; when gfs is high eight consecutive samples, a high signal is output. if gfs is low eight consecutive samples, a low signal is output. used in cav-w mode. results of measuring the disc rotational velocity. (see timing chart 2-3.) vf0 = lsb, vf7 = msb. spoa and b pin inputs. write frame clock output. high when either subcode sync s0 or s1 is detected. high when the sync protection window is open. read frame clock output. low when the built-in 16k ram exceeds the 4 frame jitter margin. peak meter register output. l0 to 7 are the left-channel and r0 to 7 are the right-channel peak data. l0 and r0 are lsb. description c1f1 0 1 1 0 0 1 no error single error correction irretrievable error c1f2 c1 correction status c2f1 0 1 1 0 0 1 no error single error correction irretrievable error c2f2 c2 correction status command bit cpusr = 1 cpusr = 0 xlon pin is high. xlon pin is low. processing
26 CXD3009Q peak meter sqso xlat sqck (peak meter) l0 l1 l2 l3 l4 l5 l6 l7 r0 r1 r2 r3 r4 r5 r6 r7 setting the soct command of $8x to 0 and the sl1 and sl0 commands of $bx to 0 and 1, respectively, results in peak detection mode. the sqso output is connected to the peak register. the maximum pcm data values (absolute value, upper 8bits) for the left and right channels can be read from sqso by inputting 16 clocks to sqck. peak detection is not performed during sqck input, and the peak register does not change during readout. this sqck input judgment uses a retriggerable monostable multivibrator with a time constant of 270s to 400s. the time during which sqck input is high should be 270s or less. also, peak detection is restarted 270s to 400s after sqck input. the peak register is reset with each readout (16 clocks input to sqck). the maximum value in peak detection mode is detected and held in this status until the next readout. when switching to peak detection mode, readout should be performed one time initially to reset the peak detection register. peak detection can also be performed for previous value hold and average value interpolation data. traverse monitor count value setting these bits are set when monitoring the traverse condition of the sens output according to the cnin frequency division. command bit 0 0 1 1 0 1 0 1 1/64 frequency division 1/128 frequency division 1/256 frequency division 1/512 frequency division trm1 xugf mnt1 rfck 47 xpck mnt0 xpck 48 gfs mnt3 xrof 49 c2po c2po gtop 50 mtsl1 0 0 1 command bit mtsl0 0 1 0 pin no. trm0 processing mode description monitor output switching the monitor output can be switched to the various signals by setting the mtsl1 and mtsl0 commands of $b.
27 CXD3009Q $cx commands clv mode gain setting: gclvs clvp mode gain setting: gmdp: gmds servo coefficient setting clv ctrl ($dx) gain mdp1 gain mdp0 gain mds1 gain mds0 gain clvs gain mds1 0 0 0 0 1 1 gain mds0 0 0 1 1 0 0 gain clvs 0 1 0 1 0 1 gclvs 12db 6db 6db 0db 0db +6db command d3 d2 d1 d0 gain mdp1 0 0 1 gain mdp0 0 1 0 gmdp 6db 0db +6db gain mds1 0 0 1 gain mds0 0 1 0 gmds 6db 0db +6db
28 CXD3009Q $dx commands command bit description tb = 0 tb = 1 tp = 0 tp = 1 bottom hold at a cycle of rfck/32 in clvs mode. bottom hold at a cycle of rfck/16 in clvs mode. peak hold at a cycle of rfck/4 in clvs mode. peak hold at a cycle of rfck/2 in clvs mode. command d3 0 tb tp gain clvs vp7 vp6 vp5 vp4 vp3 vp2 vp1 vp0 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 1 data 2 clv ctrl data 3 see the $cx commands. command bit description vp0 to 7 = f0 (h) : vp0 to 7 = e0 (h) playback at half (normal) speed to playback at normal (double) speed the rotational velocity r of the spindle can be expressed with the following equation. r = 32 256 n r: relative velocity at normal speed = 1 n: vp0 to 7 setting value note) values in parentheses are for when dspb is 1. values when crystal is 16.9344mhz and xtsl is low or when crystal is 33.8688mhz and xtsl is high. vp0 to 7 setting values are valid in cav-w mode. 2 r relative velocity [multiple] 1.5 1 0.5 f0 e0 vp0 to 7 setting value [hex] dspb = 1 dspb = 0 fig. 1-1
29 CXD3009Q $ex commands command data 1 clv mode cm3 cm2 cm1 cm0 d3 d2 d1 d0 data 2 epwm spdc icap sfsl d3 d2 d1 d0 data 3 vc2c hifc lpwr vpon d3 d2 d1 d0 command bit cm3 cm2 cm1 description spindle stop mode. ? 1 spindle forward rotation mode. ? 1 spindle reverse rotation mode. valid only when lpwr = 0, in any mode. ? 1 rough servo mode. when the rf-pll circuit isn't locked, this mode is used to pull the disc rotations within the rf- pll capture range. pll servo mode. automatic clvs/clvp switching mode. used for normal playback. 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 1 cm0 0 0 0 0 1 0 mode stop kick brake clvs clvp clva ? 1 see timing charts 1-2 to 1-6. command bit epwm spdc icap description crystal reference clv servo. used for normal-speed playback in clv-w mode. ? 2 spindle control with vp0 to 7. spindle control with the external pwm. 0 0 0 1 0 0 1 0 0 0 1 1 sfsl 0 0 0 0 vc2c 0 1 0 0 hifc 0 1 1 1 lpwr 0 0 0 0 vpon 0 0 1 1 mode clv-n clv-w cav-w cav-w ? 2 figs. 3-1 and 3-2 show the control flow with the microcomputer software in clv-w mode.
30 CXD3009Q command data 4 spd mode gain cav1 gain cav0 0 0 d3 d2 d1 d0 gain cav1 0 0 1 1 gain cav0 0 1 0 1 gain 0db 6db 12db 18db this sets the gain when controlling the spindle with the phase comparator in cav-w mode. mode clv-n clv-w cav-w lpwr 0 0 1 0 1 command kick brake stop kick brake stop kick brake stop kick brake stop kick brake stop 1-2 (a) 1-2 (b) 1-2 (c) 1-3 (a) 1-3 (b) 1-3 (c) 1-4 (a) 1-4 (b) 1-4 (c) 1-5 (a) 1-5 (b) 1-5 (c) 1-6 (a) 1-6 (b) 1-6 (c) timing chart mode clv-n clv-w cav-w lpwr 0 0 1 0 1 0 1 1-7 1-8 1-9 1-10 (epwm = 0) 1-11 (epwm = 0) 1-12 (epwm = 1) 1-13 (epwm = 1) timing chart
31 CXD3009Q timing chart 1-2 clv-n mode lpwr = 0 kick mdp h (a) kick brake mdp (b) brake stop mdp (c) stop z z l z timing chart 1-3 clv-w mode (when following the spindle rotational velocity) lpwr = 0 kick mdp h (a) kick brake mdp (b) brake stop mdp (c) stop z z l z timing chart 1-4 clv-w mode (when following the spindle rotational velocity) lpwr = 1 kick mdp h (a) kick brake mdp (b) brake z stop mdp (c) stop z z timing chart 1-5 cav-w mode lpwr = 0 kick mdp h (a) kick brake mdp (b) brake stop mdp (c) stop z l timing chart 1-6 cav-w mode lpwr = 1 kick mdp h (a) kick brake mdp (b) brake z stop mdp (c) stop z
32 CXD3009Q timing chart 1-10 cav-w mode epwm = lpwr = 0 mdp acceleration z deceleration 264khz 3.8s timing chart 1-7 clv-n mode lpwr = 0 mdp acceleration z deceleration 132khz 7.6s n 236 (ns) n = 0 to 31 timing chart 1-8 clv-w mode lpwr = 0 mdp acceleration z deceleration 264khz 3.8s timing chart 1-9 clv-w mode lpwr = 1 mdp acceleration z 264khz 3.8s the brake pulse is masked when lpwr = 1. timing chart 1-11 cav-w mode epwm = lpwr = 1 mdp acceleration z 264khz 3.8s the brake pulse is masked when lpwr = 1.
33 CXD3009Q timing chart 1-12 cav-w mode epwm = 1, lpwr = 0 pwmi mdp h l h l acceleration deceleration timing chart 1-13 cav-w mode epwm = lpwr = 1 pwmi mdp h l h z acceleration the brake pulse is masked when lpwr = 1.
34 CXD3009Q 1-2. description of sens output the following signals are output from sens, depending on the microcomputer serial register value (latching not required). note that the sens output can be read out from the sqso pin when soct = 0, sl1 = 1 and sl0 = 0. (see the $bx commands.) 2. subcode interface this section explains the subcode interface. there are two methods for reading out a subcode externally. the 8-bit subcodes p to w can be read from sbso by inputting exck to the CXD3009Q. sub q can be read out after checking the crc of the 80bits in the subcode frame. sub q can be read out from the sqso pin by inputting 80 clock pulses to the sqck pin when scor comes correctly and crcf is high. 2-1. p to w subcode readout data can be read out by inputting exck immediately after wfck falls. (see timing chart 2-1.) 2-2. 80-bit sub q readout fig. 2-1 shows the peripheral block of the 80-bit sub q register. first, sub q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the crc check circuit. 96-bit sub q is input, and if the crc is ok, it is output to sqso with crcf = 1. in addition, 80bits are loaded into the parallel/serial register. when sqso goes high 400s (monostable multivibrator time constant) or more after subcode readout, the cpu determines that new data (which passed the crc check) has been loaded. when the 80-bit data is loaded, the order of the msb and lsb is inverted within each byte. as a result, although the sequence of bytes is the same, the bits within the bytes are now ordered lsb first. once the 80-bit data load is confirmed, sqck is input so that the data can be read. the sqck input is detected, and the retriggerable monostable multivibrator is reset while the input is low. the retriggerable monostable multivibrator has a time constant from 270s to 400s. when the duration when sqck is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register. while the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register. in other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by crcok and others. (see timing chart 2-2.) the high and low intervals for sqck should be between 750ns and 120s. sein, a signal input to this lsi from the ssp, is output. low while the auto sequencer is in operation, high when operation terminates. outputs the signal input to the fok pin. normally, fok (from rf) is input. high for "focus ok". sein, a signal input to this lsi from the ssp, is output. high when the regenerated frame sync is obtained with the correct timing. low when the efm signal, after passing through the sync detection filter, is lengthened by 64 channel clock pulses or more. sens pin is fixed to low. calculates the number of tracks from the frequency division ratio set by $b.high when $c is latched; toggles each time cnin is input the number of times set in register b. sein xbusy fok sein gfs ov64 l cnin division $0x, 1x, 2x, 3x $4x $5x $6x $ax $ex $7x, 8x, 9x, bx, dx, fx $cx microcomputer serial register value (latching not required) sens output meaning
35 CXD3009Q timing chart 2-1 internal pll clock 4.3218 ? mhz wfck scor exck sbso 400ns max s0 s1 q r wfck scor exck sbso s0 s1 q r s t u v w s0 s1 p1 q r s t u v w p1 p2 p3 same same sub code p.q.r.s.t.u.v.w read timing
36 CXD3009Q fig. 2-1. block diagram subq sin a b c d e f g h (afram) h g f e d c b a (asec) (amin) 80-bit s/p register addrs ctrl 8 8 8 order inversion 8 8 8 8 8 8 si ld ld ld ld ld ld ld ld 80-bit p/s register so shift sqck crcf mix sqso mono/multi crcc subq shift
37 CXD3009Q timing chart 2-2 1 2 3 91 92 93 94 95 96 97 98 wfck scor sqso sqck mono/multi (internal) order inversion crcf1 determined by mode l crcf2 80 clock register load forbidder 270s to 400s for sqck = high 750ns to 120s 300ns max crcf adr0 adr1 adr2 adr3 ctl0 ctl1 ctl2 ctl3 sqck sqso 1 2 3
38 CXD3009Q timing chart 2-3 measurement interval (approximately 3.8s) reference window (132.2khz) measurement pulse (vcki/2) measurement counter vf0 to 7 load m the relative velocity r of the disc can be expressed with the following equation. r = (r: relative velocity, m: measurement results) vf0 to 7 is the result obtained by counting vcki/2 pulses while the reference signal (132.2khz) generated from the crystal (384fs) is high. this count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when dspb is low). m + 1 32
39 CXD3009Q 3. description of modes this lsi has three basic operating modes using a combination of spindle control and the pll. the operations for each mode are described below. 3-1. clv-n mode this mode is compatible with the cxd2507aq, and operation is the same as for the conventional control. the pll capture range is 150khz. 3-2. clv-w mode this is the wide capture range mode. this mode allows the pll to follow the rotational velocity of the disc. this rotational following control has two types: using the built-in vco2 or providing an external vco. the spindle is the same clv servo as for the conventional series. operation using the built-in vco2 is described below. (when using an external vco, input the signal from the vpco pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external vco, and input the oscillation output from the vco to the vcki pin.) while starting to rotate a disc and/or speeding up to the lock range from the condition where the disc is stopped, cav-w mode should be used. specifically, first send $e6650 to set cav-w mode and kick the disc, then send $e60c0 to set clv-w mode if alock is high, which can be read out serially from the sqso pin. clv-w mode can be used while alock is high. the microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (cav-w mode) when alock becomes low. the control flow according to the microcomputer software is shown in fig. 3-2. in clv-w mode (normal), low power consumption is achieved by setting lpwr to high. control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. however, when lpwr is set to high, deceleration pulses are not output, thereby achieving low power consumption mode. note) the capture range for clv-w mode has theoretically the range up to the signal processing limit. 3-3. cav-w mode this is cav mode. in this mode, the external clock is fixed and it is possible to control the spindle to the desired rotational velocity. the rotational velocity is determined by the vp0 to 7 setting values or the external pwm. when controlling the spindle with vp0 to 7, setting cav-w mode with the $e6650 command and controlling vp0 to 7 with the $dx commands allows the rotational velocity to be varied from low-speed to double-speed. (see the $dx commands.) also, when controlling the spindle with the external pwm, the pwmi pin is binary input which becomes kick during high intervals and brake during low intervals. the microcomputer can know the rotational velocity using v16m. the reference for the velocity measurement is a signal of 132.2khz obtained by dividing the crystal (384fs) by 128. the velocity is obtained by counting v16m/2 pulses while the reference is high, and the result is output from the new cpu interface as 8 bits (vf0 to 7). these measurement results are 31 when the disc is rotating at normal speed or 63 when it is rotating at double speed. these values match those of the 256-n for control with vp0 to 7. in cav-w mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. therefore, the cycles for the fs system clock, pcm data and all other output signals from this lsi change according to the rotational velocity of the disc (excluding dato, clko and xlto). note) the capture range for this mode is theoretically up to the signal processing limit.
40 CXD3009Q cav-w clvs clv-w clvp rotational velocity target velocity operation mode spindle mode time kick lock alock fig. 3-1. disc stop to normal condition in clv-w mode clv-w mode no yes kick $e8000 mute off $a0xxxxx alock = h ? no yes alock = l ? clv-w mode start cav-w $e6650 (clva) clv-w $e60c0 (clva) (wfck pll) fig. 3-2. clv-w mode flow chart
41 CXD3009Q 4. description of other functions 4-1. channel clock regeneration by the digital pll circuit the channel clock is necessary for demodulating the efm signal regenerated by the optical system. assuming t as the channel clock cycle, the efm signal is modulated in an integer multiple of t from 3t to 11t. in order to read the information in the efm signal, this integer value must be read correctly. as a result, t, that is the channel clock, is necessary. in an actual player, a pll is necessary to regenerate the channel clock because the fluctuation in the spindle rotation alters the width of the efm signal pulses. the block diagram of this pll is shown in fig. 4-1. the CXD3009Q has a built-in three-stage pll. the first-stage pll is a wide-band pll. when using the internal vco2, an external lpf is necessary; when not using the internal vco2, external lpf and vco are necessary. the output of this first-stage pll is used as a reference for all clocks within the lsi. the second-stage pll generates the high-frequency clock needed by the third-stage digital pll. the third-stage pll is a digital pll that regenerates the actual channel clock. a new digital pll has been provided for clv-w mode to follow the rotational velocity of the disc in addition to the conventional secondary loop.
42 CXD3009Q block diagram 4-1 x'tal xtsl osc 1/2 1/32 1/n 1/2 microcomputer control n = 1 to 256 (vp7 to 0) 1/k (ksl1, 0) clv-w cav-w spindle rotation information clv-n clv-w cav-w /clv-n phase comparator selector lpf 2/1 mux vpon 1/m 1/n vcosel2 vco2 phase comparator vco1 vcosel1 1/k (ksl3, 2) digital pll rfpll vpco vctl v16m vcki pco fili filo cltv CXD3009Q
43 CXD3009Q 4-2. frame sync protection in normal-speed playback, a frame sync is recorded approximately every 136s (7.35khz). this signal is used as a reference to recognize the data within a frame. conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. as a result, recognizing the frame sync properly is extremely important for improving playability. in the CXD3009Q, window protection and forward protection/backward protection have been adopted for frame sync protection. these functions achieve very powerful frame sync protection. there are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (wsel = 0/1). in addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. concretely, when the frame sync is being played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. if the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. in addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. 4-3. error correction in the cd format, one 8-bit data contains two error correction codes, c1 and c2. for c1 correction, the code is created with 28-byte information and 4-byte c1 parity. for c2 correction, the code is created with 24-byte information and 4-byte parity. both c1 and c2 are reed solomon codes with a minimum distance of 5. the CXD3009Q's sec strategy uses powerful frame sync protection and c1 and c2 error correction to achieve high playability. the correction status can be monitored externally. see table 4-1. when the c2 pointer is high, the data in question was uncorrectable. either the pre-value was held or an average value interpolation was made for the data. mnt3 0 0 0 1 1 1 mnt1 0 0 1 0 0 1 mnt0 0 1 1 0 1 1 description no c1 errors one c1 error corrected c1 correction impossible no c2 errors one c2 error corrected c2 correction impossible table 4-1.
44 CXD3009Q timing chart 4-1 normal-speed pb mnt3 mnt1 mnt0 t = dependent on error condition c1 correction c2 correction strobe strobe 4-4. da interface the CXD3009Q da interface is as described below. this interface includes 48 cycles of the bit clock within one lrck cycle, and is msb first. when lrck is high, the data is for the left channel.
45 CXD3009Q timing chart 4-2 lrck (44.1k) bck (2.12m) lrck (88.2k) bck (4.23m) pcmd 48-bit slot normal-speed playback 1 24 pcmd r0 lch msb (15) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 rmsb r0 lch msb (15) 24 rch msb 2 3 4 5 6 7 8 9 10 11 12 48-bit slot double-speed playback 12 l0
46 CXD3009Q 4-5. digital out there are three digital out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. the CXD3009Q supports type 2 form 1. sub q data which are matched twice in succession after a crc check are input to the first four bits (bits 0 to 3) of the channel status. table 4-2. 4-6. servo auto sequence this function performs a series of controls, including auto focus and track jumps. when the auto sequence command is received from the cpu, auto focus, 1-track jump, 2n-track jumps, and n-track move are executed automatically. ssp (servo signal processor lsi) is used in an exclusive manner during the auto sequence execution (when xbusy = low), so that commands from the cpu are not transferred to the ssp, but can be sent to the CXD3009Q. connect the cpu, rf and ssp as shown in fig. 4-2. when clok goes from low to high while xbusy is low, xbusy does not become high for a maximum of 100s after that point. this is to prevent the transfer of erroneous data to the ssp when xbusy changes from low to high by the monostable multivibrator, which is reset by clok being low (when xbusy is low). 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 0 id0 id1 copy emph 0 0 0 0 1 0 0 0 0 0 0 0 from sub q 0 16 32 48 176 bits 0 to 3...sub q control bits that matched twice with crcok bit 29..........1 when vpon is 1 digital out c bit 12 34 56 78 9101112131415
47 CXD3009Q (a) auto focus ($47) focus search-up is performed, fok and fzc are checked, and the focus servo is turned on. if $47 is received from the cpu, the focus servo is turned on according to fig. 4-3. the auto focus starts with focus search-up, and the pickup should be lowered beforehand (focus search-down). in addition, blind e of register 5 is used to eliminate fzc chattering. in other words, the focus servo is turned on at the falling edge of fzc after fzc has been continuously high for a longer time than e. connection diagram for using auto sequencer (example) fig. 4-2. fig. 4-3-(a). auto focus flow chart rf fok ssp c. out sens data clk xlt cnin fok data clok xlat sens microcomputer CXD3009Q sein dato clko xlto auto focus focus search up fok = h no yes fzc = h no yes fzc = l no yes end focus servo on (checks whether fzc is continuously high for the period of time e set with register 5)
48 CXD3009Q fig. 4-3-(b). auto focus timing chart (b) track jump 1, 10, and 2n-track jumps are performed respectively. always use this when the focus, tracking, and sled servos are on. note that tracking gain-up and braking-on should be sent beforehand because they are not involved in this sequence. 1-track jump when $48 ($49 for rev) is received from the cpu, a fwd (rev) 1-track jump is performed in accordance with fig. 4-4. set blind a and brake b with register 5. 10-track jump when $4a ($4b for rev) is received from the cpu, a fwd (rev) 10-track jump is performed in accordance with fig. 4-5. the principal difference from the 1-track jump is to kick the sled. in addition, after kicking the actuator, when 5 tracks have been counted through cnin, the brake is applied to the actuator. then, when the actuator speed is found to have slowed up enough (determined by the cnin cycle becoming longer than the overflow c set with register 5), the tracking and sled servos are turned on. 2n-track jump when $4c ($4d for rev) is received from the cpu, a fwd (rev) 2n-track jump is performed in accordance with fig. 4-6. the track jump count n is set with register 7. although n can be set to 2 16 tracks, note that the setting is actually limited by the actuator. cnin is used for counting the number of jumps. although the 2n-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "d", set with register 6. n-track move when $4e ($4f for rev) is received from the cpu, a fwd (rev) n-track move is performed in accordance with fig. 4-7. n can be set to 216 tracks. cnin is used for counting the number of jumps. this n-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. xlt fok sein (fzc) busy command for ssp $47latch $03 blind e $08
49 CXD3009Q fig. 4-4-(a). 1-track jump flow chart track no yes end track fwd kick sled servo off wait (blind a) cnin = track rev kick wait (brake b) track, sled servo on (fwd kick for rev jump) (rev kick for rev jump) fig. 4-4-(b). 1-track jump timing chart xlt cnin busy command for ssp $48 (rev = $49) latch $28 ($2c) blind a brake b $2c ($28) $25
50 CXD3009Q fig. 4-5-(a). 10-track jump flow chart 10 track no yes end track, sled fwd kick wait (blind a) cnin = 5 ? track, rev kick track, sled servo on (checks whether the cnin cycle is longer than overflow c) (counts cnin 5) no yes c = overflow ? fig. 4-5-(b). 10-track jump timing chart xlt cnin busy $4a (rev = $4b) latch blind a $2a ($2f) cnin 5 count $2e ($2b) overflow c $25 command for ssp
51 CXD3009Q fig. 4-6-(a). 2n-track jump flow chart 2n track no yes end track, sled fwd kick wait (blind a) cnin = n track rev kick track servo on no yes c = overflow wait (kick d) sled servo on fig. 4-6-(b). 2n-track jump timing chart xlt cnin busy command for ssp blind a $2a ($2f) cnin n count $2e ($2b) overflow kick d $26 ($27) $25 $4c (rev = $4d) latch
52 CXD3009Q fig. 4-7-(a). n-track move flow chart n track move no yes end track servo off sled fwd kick wait (blind a) cnin = n end track, sled servo off fig. 4-7-(b). n-track move timing chart xlt cnin busy command for ssp $22 ($23) blind a cnin n count $20 $4e (rev = $4f) latch
53 CXD3009Q 4-7. digital clv fig. 4-8 shows the block diagram. digital clv outputs mds error and mdp error signals with pwm, with the signal sampling frequency increased up to 130khz during normal-speed playback in clvs, clvp and other modes. in addition, the digital spindle servo gain is variable. digital clv clvs u/d mds error mdp error clv p/s measure measure 2/1 mux over sampling filter-1 gain mds 1/2 mux clv p/s over sampling filter-2 noise shape modulation kick, brake, stop mdp mode select gain mdp lpwr pwmi fig. 4-8. block diagram clvs u/d: up/down signal from clvs servo mds error: frequency error for clvp servo mdp error: phase error for clvp servo pwmi: spindle drive signal from the microcomputer for cav servo
54 CXD3009Q 4-8. asymmetry compensation rf r1 r1 asyo asyi r1 2 r2 5 = bias r1 r1 r2 CXD3009Q 46 47 35 36 fig. 4-9. example of asymmetry compensation application circuit 4-9. cd-text data demodulation in order to demodulate the cd-text data, set data 6 d3 txon command of $8 to 1. during txon = 1, the exck pin should be set to low and the sbso output data should not be used because the cd-text demodulation circuit uses exck and sbso exclusively. it requires 26.7ms (max.) to demodulate the cd-text data properly after txon is set to 1. the cd-text data is output after the sqso pin is switched by the command. the cd-text data can be output by setting data 6 d2 txout command of $8 to 1. the readout clock should be input to sqck in order to read the data. the data which can be read out is the crc calculation results for each pack (crc), cd-text data excluding crc data (16 bytes). when the cd-text data is read, the order of the msb and lsb is inverted within each byte. as a result, although the sequence of bytes is the same, the bits within the bytes are now ordered lsb first. the data which can be stored in the ic is for 1 packet (4 packs). fig. 4-10. cd-text demodulation circuit block diagram txon exck sbso sqck sqso txout subcode decoder cd-text decoder
55 CXD3009Q crc 4 crc 3 crc 2 crc 1 0 000 s2 r2 w1 v1 u1 t1 s1 r1 u3 t3 s3 r3 w2 v2 u2 t2 w4 v4 u4 t4 s4 crc data id1 (pack1) id2 (pack1) id3 (pack1) 16byte 16byte 16byte 16byte 4bit 4bit subcode q data scor txout (command) sqck sqso sqck txout (command) lsb msb lsb msb lsb crc 0 pack1 pack2 pack3 pack4 crcf crcf 80 clock sqso 520 clock fig. 4-11. cd-text data timing chart
56 CXD3009Q 5. 1bit dac block 5-1. dac block input timing timing chart 5-1 shows the input timing for the dac block. the data from the cd signal processor block to the dac block can be connected inside the ic by setting the outl command of $8x to 1. set outl1 to 0 when the data is send to the dac block via the audio dsp and the like. 5-2. description of dac block functions zero data detection when the condition where the lower 4bits of the input data are dc and the remaining upper bits are all "0" or all "1" has continued for approximately 300ms, zero data is detected. zero data detection is performed independently for the left and right channels. mute flag output the lmut and rmut pins go active when any one of the following conditions is met. the polarity can be selected by the zdpl command of $9x. when zero data is detected when a high signal is input to the sysm pin when the smut command of $ax is set attenuation operation assuming attenuation data x1, x2 and x3 (x1 > x3 > x2), the corresponding audio outputs are y1, y2 and y3 (y1 > y3 > y2). first, x1 is sent, followed by x2. if x2 is sent before x1 reaches y1 (a in the figure), x1 continues approaching y2. next, if x3 is sent before x1 reaches y2 (b or c in the figure), x1 then approaches y3 from the value (b or c in the figure) at that point. a y1 b y3 c y2 23.2 [ms] 00 (h) 0db 7f (h)
57 CXD3009Q dac block mute operation soft mute soft mute results and the input data is attenuated to zero when any one of the following conditions is met. when attenuation data of "000" (high) is set when the smut command of $ax is set to 1 when a high signal is input to the sysm input pin forced mute forced mute results when the fmut command of $ax is set to 1. forced mute fixes the pwm output that is input to the lpf block to low. ? when setting fmut, set opsl2 to 1. (see the $ax commands.) zero detection mute forced mute is applied when the zmut command of $9x is set to 1 and the zero data is detected for the left and right channels. (see "zero data detection".) soft mute on soft mute off soft mute off 23.2 [ms] 23.2 [ms] 0db db
58 CXD3009Q input timing for dac block normal-speed playback lrcki (44.1k) bcki (2.12m) 1 24 pcmdi r0 lch msb (15) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 rmsb pcmdi lrcki (88.2k) bcki (4.23m) double-speed playback 24 r0 lch msb (15) rch msb 234 56789101112 1 2 l0 timing chart 5-1
59 CXD3009Q normal dbb mid dbb max 10.00 4.00 6.00 4.00 2.00 0.00 2.00 8.00 6.00 8.00 10.00 12.00 14.00 10 30 100 300 1k 3k 10k 30k digital bass boost frequency response [hz] [db] graph 5-2. lrck synchronization synchronization is performed at the first falling edge of the lrck input during reset. after that, synchronization is lost when the lrck input frequency changes and resynchronization must be performed. the lrck input frequency changes when the master clock of the lsi is switched and the playback speed changes such as the following cases. when the xtsl pin switches between high and low when the dspb command of $9x setting changes when the mcsl command of $9x setting changes lrck switching may also be performed if there are other ics between the cd-dsp block and the dac block. resynchronization must be performed in this case as well. for resynchronization, set the lrwo command of $ax to 1, wait for one lrck cycle or more, and then set lrwo to 0. ? when setting lrwo, set opsl2 to 1. (see the $ax commands.) sycof when lrck, pcmd and bck are connected directly with lrcki, pcmdi and bcki, respectively, playback can be performed easily in cav-w mode by setting sycof of address 9 to 1. normally, the memory proof, etc., is used for playback in cav-w mode. in cav-w mode, the lrck output conforms not to the crystal but to the vco. therefore, synchronization is frequently lost. setting sycof of address 9 to 1 ignores that the lrcki input synchronization is lost, facilitating playback. however, the playback is not perfect because pre-value hold or data skip occurs due to the wow flutter in the lrcki input. ? set sycof to 0 except when connecting lrck, pcmd and bck directly with lrcki, pcmdi and bcki, respectively, and performing playback in cav-w mode. ? set sycof to 0 in advance when lrck resynchronization is applied with lrwo=1. digital bass boost bass boost without external parts is possible using the built-in digital filter. the boost strength has two levels: mid. and max. bsbst and bbsl of address a are used for the setting. see graph 5-2 for the digital bass boost frequency response.
60 CXD3009Q analog out c2 680p 12k 12k 12k c1 150p aout1 (2) ain1 (2) lout1 (2) vc fig. 6-1. lpf external circuit 6. lpf block the CXD3009Q contains an initial-stage secondary active lpf with numerous resistors and capacitors and an operational amplifier with reference voltage. the resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. the reference voltage (v c ) is (av dd av ss )/2. the lpf block application circuit is shown below. in this circuit, the cut-off frequency is fc 40khz. the external capacitors' values when fc = 30khz and 50khz are noted below as a reference. the resistors' values do not change at this time. ? when fc 30khz: c1 = 200pf, c2 = 910pf when fc 50khz: c1 = 120pf, c2 = 560pf lpf block application circuit
61 CXD3009Q 7. setting method of the CXD3009Q playback speed (in clv-n mode) (a) cd-dsp block the playback modes shown below can be selected by the combination of the crystal, xtsl pin and dspb command of $9x. cd-dsp block playback speed x'tal 768fs 768fs 384fs 384fs 384fs 1 1 0 0 1 0 1 0 1 1 1 2 1 2 1 ? 1 xtsl dspb cd-dsp block playback speed fs = 44.1khz ? 1 low power consumption mode. the cd-dsp processing speed is halved, allowing the power consumption to be decreased. (b) 1-bit dac block the operating speed of the dac block is determined by the crystal and the mcsl command of $9x regardless of the operating conditions of the cd-dsp block mentioned above. this allows the playback mode for the dac block and cd-dsp block to be set independently. 1-bit dac block playback speed x'tal 768fs 768fs 384fs 1 0 0 1 2 1 mcsl dac block playback speed fs = 44.1khz
62 CXD3009Q application circuit rf driver sens fok xrst xlat data clk gfs sqso sqck scor mute v dd vss ls ssp 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 v dd sysm avss av dd aout1 ain1 lout1 avss xv dd xtai xtao xvss avss lout2 ain2 aout2 av dd avss xrst v dd 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 vss exck sbso emphi dout c4m pcmd xpck xugf v dd vss bcki bck scor wfck c2po gfs emph xtsl pcmdi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 lmut sens xlat sqso rmut sqck data sein vss clok vss cnin dato xlto clko spoa spob xlon fok v dd 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 avss fili lrcki lrck asyo asyi bias rf av dd cltv mdp filo pco vctl v16m vcki vpco pwmi tes1 test application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
63 CXD3009Q package outline unit: mm sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy qfp-80p-l03 lqfp080-p-1414 0.6g 80pin qfp (plastic) 16.0 0.4 14.0 0.1 + 0.4 0.3 0.1 + 0.15 0 to 10 0.5 0.2 0.1 0.1 + 0.15 (15.0) 0.127 0.05 + 0.1 1.5 0.15 + 0.35 40 21 20 1 41 60 61 80 m 0.12 0.1 0.65 sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin copper alloy qfp-80p-l03 p-qfp80-14x14-0.65 0.6g 80pin qfp (plastic) 16.0 0.4 14.0 ?0.1 + 0.4 b 0? to 10? 0.5 0.2 0.1 ?0.1 + 0.15 (15.0) 1.5 ?0.15 + 0.35 40 21 20 1 41 60 61 80 m 0.24 0.1 0.65 b = 0.3 0.03 0.125 0.04 detail a : palladium a palladium plating
64 CXD3009Q 16.0 0.2 14.0 0.1 1 20 21 40 41 60 61 80 1.6max 1.4 (15.0) a b 0.1 s s package material lead treatment lead material package mass epoxy resin 42 alloy package structure sony code eiaj code jedec code qfp-80p-l052 p-qfp80-14x14-0.65 solder plating detail a 0.17 0.05 detail b 80pin qfp (plastic) + 0.03 0.65 b m 0.1 s 1.6 g 0.1 0.1 0 to 10 0.5 0.15 b = 0.32 0.1 sony corporation

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